1. Field of the Invention
The present invention relates to a variable-gain integrator for accumulating and adding input data.
2. Description of Related Art
Integrators formed by a digital circuit are known. An example structure of such a digital integrator is shown in FIG. 13. Referring to FIG. 13, input data and data stored in a flip-flop (hereinafter referred to as FF) 72 are added by an adder 71, and the added data are stored in FF 72 at the next clock. As a result of repetition of this operation, the input data are accumulated and added up to thereby provide integration data. As the bit width of a bus and the number of bits of FF 72 are generally fixed in a digital circuit, in the example shown in FIG. 13, a clip circuit 73 is provided for clipping, thereby limiting the range of data after addition.
Multiplication of the integration data obtained through accumulation and addition by the gain before being output is often desirable. FIG. 14 shows a possible integrator structure in which integration data are multiplied by gain and then output. Referring to FIG. 14, a multiplier 74 multiplies integration data output from a clip circuit 73 provided at a point A, by gain G. The data output from the multiplier 74 are limited to the bit width j of the output bus by a clip circuit 75 provided at a point B.
The integrator shown in FIG. 14, however, suffers from a problem when the gain of the multiplier 74 is variable, as will be described using an example in which the bit width of the output bus is 4 and gain of the multiplier is variable among 1/16, ⅛, and ¼.
When the number of bits of FF 72 is set to 8 bits, the maximum value of the integration data (output data from the clip circuit 73) is 255 (“11111111” in binary). When the gain of the multiplier 74 is 1/16, the maximum output data value of the multiplier 74 is 15 (binary “1111”), which needs no clipping operation after the multiplication. When the gain is ⅛, the maximum output data value of the multiplier 74 is 31 (“11111”), and a clipping operation is required when the first higher bit is “1”. When the gain is ¼, the maximum output data value of the multiplier 74 is 63 (“111111”), and a clipping operation is required when the first or second higher bit is “1”. Accordingly, a clip circuit 75 for clipping after multiplication is required in addition to the clip circuit 73 for clipping after addition. Moreover, the clip circuit 75 used for clipping after multiplication must perform different clipping operations depending on the gain. As a result, a complicated circuit structure is required for an integrator as a whole.
On the other hand, when the number of bits of FF 72 is set to 6, the maximum value for the integration data is 63 (“111111” in binary number). In this case, the maximum output data values of the multiplier 74 are 3 (“0011”), 7 (“0111”), and 15 (“1111”) when the gain of the multiplier 74 is 1/16, ⅛, and ¼, respectively. Accordingly, no clipping operations are necessary regardless of the gain. In this case, however, the data after multiplication range from 0 to 3 when the gain of the multiplier 74 is 1/16 and from 0 to 7 when the gain is ⅛, which are narrower than the data range, 1 to 15, of the output bus. Consequently, even when the maximum value 63 (“111111”) is obtained as the integration data due to clipping in the clip circuit 73, the output data of the multiplier 74 becomes 3, which is too much smaller than the maximum value 15 of the output bus, when the gain of the multiplier 74 is 1/16.